Studying at York
Digital Design - ELE00147M
- Department: Electronic Engineering
- Credit value: 20 credits
- Credit level: M
- Academic year of delivery: 2023-24
Module summary
This module introduces students to digital design concepts along with the appropriate role of Hardware Description Languages (HDLs) in the modern digital design flow. Particular emphasis will be placed on using HDLs for the synthesis of digital circuits and on the development of appropriate testing through the use of HDL testbenches and simulation. The module will then progress to a detailed analysis of the operation and structure of microprocessors, including the design of a simple RISC architecture using HDL.
Module will run
| Occurrence | Teaching period |
|---|---|
| A | Semester 1 2023-24 |
Module aims
Subject content aims:
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To introduce the concept and operation of hardware description languages (HDLs) and HDL-based modern digital design flow.
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To re-establish digital design’s fundamental principles: combinational and sequential logic, finite state machines, and computation building blocks
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To introduce to the concept of finite state machines with a datapath
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To analyse in depth the operation and structure of microprocessors, including datapath, control, memory subsystem and peripherals
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To provide practical experience of working through design problems using modern CAD tools
Graduate skills aims:
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To develop skills in critically evaluating and synthesising new information based on researched information and writing concise technical reports appropriate for the target audience
Module learning outcomes
Subject content learning outcomes
After successful completion of this module, students will:
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Be able to describe the digital design concepts and their relationship to practical design
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Understand principles of various components and know how to use them
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Be able to design and simulate a variety of digital circuits with HDL
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Be able to design, implement and test general-purpose and application-specific processor architectures
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Be able to use modern CAD tools for design capture, modelling, simulation, synthesis, functional verification and other aspects of the digital design flow.
Graduate skills learning outcomes
After successful completion of this module, students will:
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Be able to construct concise technical reports that critically evaluate and synthesise new information based on research, appropriate for the target audience
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To develop individual and group skills in the design, test, and verification of digital circuits
Indicative assessment
| Task | % of module mark |
|---|---|
| Essay/coursework | 30 |
| Essay/coursework | 40 |
| Essay/coursework | 30 |
Special assessment rules
None
Additional assessment information
The reports consist, for the most part, of HDL code and simulations screenshots. They allow formative feedback to be given at each stage as the work builds into a larger project. Submissions consist of code, simulation screenshots and additional screenshots as well as occasional comments and questions.
Indicative reassessment
| Task | % of module mark |
|---|---|
| Essay/coursework | 30 |
| Essay/coursework | 70 |
Module feedback
'Feedback’ at a university level can be understood as any part of the learning process which is designed to guide your progress through your degree programme. We aim to help you reflect on your own learning and help you feel more clear about your progress through clarifying what is expected of you in both formative and summative assessments. A comprehensive guide to feedback and to forms of feedback is available in the Guide to Assessment Standards, Marking and Feedback.
The School of PET aims to provide some form of feedback on all formative and summative assessments that are carried out during the degree programme. In general, feedback on any written work/assignments undertaken will be sufficient so as to indicate the nature of the changes needed in order to improve the work. The School will endeavour to return all exam feedback within the timescale set out in the University's Policy on Assessment Feedback Turnaround Time. The School would normally expect to adhere to the times given, however, it is possible that exceptional circumstances may delay feedback. The School will endeavour to keep such delays to a minimum. Please note that any marks released are subject to ratification by the Board of Examiners and Senate. Meetings at the start/end of each term provide you with an opportunity to discuss and reflect with your supervisor on your overall performance to date.
Indicative reading
TBC