- Department: Electronic Engineering
- Credit value: 20 credits
- Credit level: H
- Academic year of delivery: 2024-25
- See module specification for other years: 2023-24
The module will introduce tools and methodologies for the design and implementation of advanced digital circuits, covering technology and design flows targeting application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs). Techniques to improve performance will be considered at different levels. Technology scaling, performance (timing)/power/area (PPA), standard cell libraries, full-/semi-custom ASIC design. Timing, pipelining, clock domain crossing, place and route on FPGA. Approaches for designing testable circuits will be developed, including verification, fault models, design for testability. Where possible, concepts will be implemented in lab exercises.
Pre-requisite modules
Co-requisite modules
- None
Prohibited combinations
- None
Occurrence | Teaching period |
---|---|
A | Semester 2 2024-25 |
Subject content aims:
Graduate skills aims:
Subject content learning outcomes
After successful completion of this module, students will:
Be able to use and understand the complete design flow (synthesis, place and route, floor-planning, timing analysis, etc.) required to implement complex digital designs
Be able to implement, characterise and use digital standard cells and simple circuits within an ASIC design.
Be able to implement and use complex IP modules within a FPGA design
Understand and describe advanced circuit design techniques
Be able to develop complex testbenches for circuit verification and devise appropriate verification strategies, including post and pre route simulation
Appreciate the strengths and limitations of fault modelling and detection in digital circuits and integrate test logic in a design
Graduate skills learning outcomes
After successful completion of this module, students will:
Be able to concisely and accurately report the results of experiments.
Topics covered include:
ASIC vs. FPGA technology
Performance characterization at digital cell level
Digital standard cell libraries
Full-/Semi-custom design
Performance and metrics for digital circuits
Testing and design for testability
Synchronisation and clock domains
Variability and timing closure
Advanced computer architectures
Task | % of module mark |
---|---|
Essay/coursework | 25 |
Essay/coursework | 25 |
Essay/coursework | 25 |
Essay/coursework | 25 |
None
The reports consist, for the most part, of schematics, HDL code and simulations screenshots. They allow formative feedback to be given at each stage.
Task | % of module mark |
---|---|
Essay/coursework | 75 |
Essay/coursework | 25 |
'Feedback’ at a university level can be understood as any part of the learning process which is designed to guide your progress through your degree programme. We aim to help you reflect on your own learning and help you feel more clear about your progress through clarifying what is expected of you in both formative and summative assessments. A comprehensive guide to feedback and to forms of feedback is available in the Guide to Assessment Standards, Marking and Feedback.
The School of PET aims to provide some form of feedback on all formative and summative assessments that are carried out during the degree programme. In general, feedback on any written work/assignments undertaken will be sufficient so as to indicate the nature of the changes needed in order to improve the work. The School will endeavour to return all exam feedback within the timescale set out in the University's Policy on Assessment Feedback Turnaround Time. The School would normally expect to adhere to the times given, however, it is possible that exceptional circumstances may delay feedback. The School will endeavour to keep such delays to a minimum. Please note that any marks released are subject to ratification by the Board of Examiners and Senate. Meetings at the start/end of each term provide you with an opportunity to discuss and reflect with your supervisor on your overall performance to date.
TBC